Title :
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor
Author :
Suzuki, Kazumasa ; Yamashina, Masakazu ; Nakayama, Takashi ; Izumikawa, Masanori ; Nomura, Masahiro ; Igura, Hiroyuki ; Heiuchi, Hideki ; Goto, Junichi ; Inoue, Toshiaki ; Koseki, Youich ; Abiko, Hitoshi ; Okabe, Kazuhiro ; One ; Yano, Youich ; Yamada, Ha
Author_Institution :
Microelectronics Res. Labs., NEC Corp., Kanagawa, Japan
fDate :
12/1/1994 12:00:00 AM
Abstract :
A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm×8.84 mm die area with 0.4 μm CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage
Keywords :
CMOS digital integrated circuits; large scale integration; microprocessor chips; pipeline processing; reduced instruction set computing; synchronisation; 0.4 micron; 1 kbyte; 3.3 V; 32 bit; 500 MHz; 6 W; 8-stage pipelined architecture; CMOS RISC processor; LSI chip; PLL frequency multiplier; clock synchronization circuit; double-stage pipelined cache; high-speed circuits; look-ahead carry adder circuit; phase locked loop; small-skew clock distribution method; stacked power-line structure; Adders; CMOS process; CMOS technology; Circuits; Clocks; Frequency locked loops; Microprocessors; Phase locked loops; Reduced instruction set computing; Registers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
