Title :
SAT-based unbounded symbolic model checking
Author :
Kang, Hyeong-Ju ; Park, In-Cheol
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
This paper describes a Boolean satisfiability checking (SAT)-based unbounded symbolic model-checking algorithm. The conjunctive normal form is used to represent sets of states and transition relation. A logical operation on state sets is implemented as an operation on conjunctive normal form formulas. A satisfy-all procedure is proposed to compute the existential quantification required in obtaining the preimage and fix point. The proposed satisfy-all procedure is implemented by modifying a SAT procedure to generate all the satisfying assignments of the input formula, which is based on new efficient techniques such as line justification to make an assignment covering more search space, excluding clause management, and two-level logic minimization to compress the set of found assignments. In addition, a cache table is introduced into the satisfy-all procedure. It is a difficult problem for a satisfy-all procedure to detect the case that a previous result can be reused. This paper shows that the case can be detected by comparing sets of undetermined variables and clauses. Experimental results show that the proposed algorithm can check more circuits than binary decision diagram-based and previous SAT-based model-checking algorithms.
Keywords :
Boolean functions; circuit analysis computing; formal verification; integrated circuit testing; symbol manipulation; Boolean satisfiability checking; SAT-based unbounded symbolic model checking; cache table; conjunctive normal form formulas; formal verification; logical operation; satisfy-all procedure; search space; state sets; symbol manipulation; transition relation; two-level logic minimization; Algorithm design and analysis; Boolean functions; Circuits; Data structures; Equations; Explosions; Formal verification; Logic; Minimization; System-on-a-chip;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2004.841068