DocumentCode
1215392
Title
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits
Author
Takahashi, Hiroshi ; Keller, Keith J. ; Le, Kim T. ; Saluja, Kewal K. ; Takamatsu, Yuzo
Author_Institution
Dept. of Comput. Sci., Ehime Univ., Japan
Volume
24
Issue
2
fYear
2005
Firstpage
252
Lastpage
263
Abstract
We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS´89 and ITC´99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.
Keywords
crosstalk; fault simulation; logic testing; sequential circuits; false crosstalk faults; synchronous sequential circuits; target crosstalk faults; timing information; topological information; Benchmark testing; Central Processing Unit; Circuit faults; Circuit testing; Crosstalk; Delay effects; Fault diagnosis; Sequential analysis; Sequential circuits; Timing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2004.837733
Filename
1386380
Link To Document