A proposed SEU tolerant dynamic random access memory (DRAM) cell

Author

Agrawal, Ghasi R. ; Massengill, Lloyd W. ; Gulati, Kush

Author_Institution

Dept. of Electr. and Comput. Eng., Vanderbilt Univ., Nashville, TN, USA

Volume

41

Issue

6

fYear

1994

Firstpage

2035

Lastpage

2042

Abstract

A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a self-compensating state while the cell is in standby mode. The proposed cell is comparable in size to a conventional DRAM cell, and computer simulations show an improvement in critical charge of two orders of magnitude over conventional 1-T DRAM cells.<>

Keywords

CMOS memory circuits; DRAM chips; alpha-particle effects; errors; radiation hardening (electronics); SEU tolerant DRAM cell; bootstrapped storage capacitor; dynamic RAM; dynamic random access memory; integrated breakdown diode; n-channel access transistor; self-compensating state; single event cell errors; single event upset; standby mode; Capacitors; Corporate acquisitions; DRAM chips; Diodes; Electric breakdown; Electric resistance; Integrated circuit technology; Random access memory; Single event upset; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.340539

Filename

340539