• DocumentCode
    1215752
  • Title

    SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell

  • Author

    Alles, Michael L.

  • Author_Institution
    Ibis Technol. Corp., Danvers, MA, USA
  • Volume
    41
  • Issue
    6
  • fYear
    1994
  • Firstpage
    2093
  • Lastpage
    2097
  • Abstract
    SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.<>
  • Keywords
    CMOS memory circuits; SPICE; SRAM chips; carrier lifetime; circuit analysis computing; errors; integrated circuit modelling; minority carriers; radiation effects; radiation hardening (electronics); silicon-on-insulator; 6-T SRAM cell; CMOS SRAM cell; SEU sensitivity; SPICE analysis; Si; fully depleted SOI CMOS technology; minority carrier lifetime; parasitic bipolar gain; static RAM; CMOS technology; Charge carrier lifetime; Circuit simulation; Doping; MOSFETs; Random access memory; SPICE; Silicon on insulator technology; Single event upset; Space technology;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.340547
  • Filename
    340547
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1215752