• DocumentCode
    1216051
  • Title

    SEU immunity: The effects of scaling on the peripheral circuits of SRAMs

  • Author

    Jacunski, L. ; Doyle, S. ; Jallic, D. ; Haddad, N. ; Scott, T.

  • Author_Institution
    Loral Federal Syst., Manassas, VA, USA
  • Volume
    41
  • Issue
    6
  • fYear
    1994
  • Firstpage
    2272
  • Lastpage
    2276
  • Abstract
    Heavy ion testing on a scaled 256 K SRAM has shown that SEU analysis of the peripheral circuits as well as the memory cell must be performed as circuits are scaled to smaller and smaller dimensions. This paper describes the SEU, induced phenomena experienced by the scaled version of a previous 256 K radiation hardened SRAM design, affected by circuits in the periphery.<>
  • Keywords
    CMOS memory circuits; SRAM chips; integrated circuit testing; ion beam effects; radiation hardening (electronics); 256 Kbit; CMOS; SEU immunity; SRAMs; heavy ion testing; peripheral circuits; radiation hardened design; scaling; CMOS technology; Circuit testing; Decoding; Inverters; Performance evaluation; Radiation hardening; Random access memory; Resistors; Single event upset; Switches;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.340575
  • Filename
    340575
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1216051