A modified architecture used for input matching in CMOS low-noise amplifiers

An architecture used for input matching in CMOS low-noise amplifiers (LNAs) is investigated in this paper. In the proposed architecture, gate and source inductors, which are essential in the traditional source inductive degeneration CMOS LNAs, are either reduced or removed. The architecture is finally verified by a narrow-band LNA and a wide-band LNA operating at 2.4-2.5 and 5.1-5.9 GHz, respectively. The narrow-band LNA has measured power gain of 24-dB, noise figure (NF) of 2.6-2.8 dB, and power consumption of 15 mW. The wide-band LNA provides 22.6-24.6-dB power gain and 2.85-3.5-dB NF while drawing 6 mA current from a 1.5-V voltage supply. Compared with their traditional counterparts, the proposed LNAs consume less chip area and present better gain performance.