System-level test and yield improvement for optoelectronic-VLSI chips

Author

Thibodeau, Jean-Philippe ; Venditti, Michael B. ; Plant, David V.

Author_Institution

Electr. & Comput. Eng. Dept., McGill Univ., Montreal, Que., Canada

Volume

52

Issue

11

fYear

2005

Firstpage

794

Lastpage

797

Abstract

Some of the unique issues involved in testing transmitter and receiver circuits for optoelectronic-very-large-scale-integrated (OE-VLSI) applications are reviewed. In particular, the problem of testing OE-VLSI chips prior to optoelectronic device integration is outlined. Based on circuit-level approaches such as fault sensitization and novel system-level testing methodologies, the first OE-VLSI chip with testable transmitters, receivers and digital circuitry was designed in 0.35-μm CMOS. The operation of the ASIC was verified experimentally and a fault-coverage greater than 80% is obtained, for a test time in the hundreds of microseconds range. Yield improvements ranging from 10% to 25% are predicted.

Keywords

CMOS digital integrated circuits; VLSI; design for testability; fault simulation; integrated circuit testing; integrated circuit yield; integrated optoelectronics; 0.35 micron; design for testability; fault diagnosis; fault sensitization; optoelectronic-VLSI chips; receiver circuits; system-level test; transmitter circuits; very large scale integration; yield estimation; yield improvement; Application specific integrated circuits; Circuit faults; Circuit testing; Fault detection; Fault diagnosis; Optical receivers; Optical transmitters; Optoelectronic devices; System testing; Transceivers; Design for testability; fault diagnosis; optoelectronic devices; optoelectronic-very-large-scale integration (OE-VLSI); yield estimation;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2005.852531

Filename

1532458