DocumentCode
1216493
Title
A methodology for the identification of worst-case test vectors for logical faults induced in CMOS circuits by total dose
Author
Abou-Auf, A.A. ; Barbe, D.F. ; Eisen, H.A.
Author_Institution
US Army Res.Lab., Adelphi, MD, USA
Volume
41
Issue
6
fYear
1994
Firstpage
2585
Lastpage
2592
Abstract
A new methodology was developed for the identification of the worst-case combination of irradiation and postirradiation test vectors. The methodology significantly simplifies total-dose testing of CMOS VLSI devices. It also provides more accurate assessment of failure levels for such devices.<>
Keywords
CMOS integrated circuits; VLSI; integrated circuit reliability; integrated circuit testing; CMOS VLSI devices; CMOS circuits; failure levels; irradiation; logical faults; postirradiation test vectors; total dose; total-dose testing; worst-case test vectors; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Failure analysis; Fault diagnosis; Inverters; Logic testing; Observability; Very large scale integration;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/23.340619
Filename
340619
Link To Document