Title :
A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces
Author :
Chappell, Terry I. ; Schuster, Stanley E. ; Chappell, Barbara A. ; Allan, J.W. ; Sun, Jack Y -C ; Klepner, Stephen P. ; Franch, Robert L. ; Greier, Paul F. ; Restle, Phillip J.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
8/1/1989 12:00:00 AM
Abstract :
A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 μm Leff, self-aligned TiSi2 double-level metal, and an average minimum feature size of 1.35 μm. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; 1.35 micron; 3.5 ns; 300 K; 6.2 ns; 64 Kbit; 77 K; CMOS RAM; ECL interfaces; LN-temperature operation; TiSi2; access times; channel length; circuit-device interactions; double-level metal; minimum feature size; power supply sensitivities; velocity saturation effects; BiCMOS integrated circuits; CMOS process; CMOS technology; Driver circuits; Nitrogen; Power supplies; Read-write memory; Signal design; Temperature; Time measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
