DocumentCode :
1216579
Title :
Logic synthesis and verification [Book Review]
Volume :
19
Issue :
3
fYear :
2003
fDate :
5/1/2003 12:00:00 AM
Firstpage :
41
Lastpage :
41
Keywords :
Binary decision diagrams; Book reviews; Boolean functions; Circuit synthesis; Data structures; Digital signal processing; Logic circuits; Minimization methods; Optimization methods; Timing;
fLanguage :
English
Journal_Title :
Circuits and Devices Magazine, IEEE
Publisher :
ieee
ISSN :
8755-3996
Type :
jour
DOI :
10.1109/MCD.2003.1203179
Filename :
1203179
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1216579
