A new CR-delay circuit technology for high-density and high-speed DRAMs

Author

Watanabe, Yohji ; Ohsawa, Takashi ; Sakurai, Kiyofumi ; Furuyama, Tohru

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

24

Issue

4

fYear

1989

fDate

8/1/1989 12:00:00 AM

Firstpage

905

Lastpage

910

Abstract

The capacitance-resistance (CR) delay circuit technology assures full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions and thus realizes a fast access time. A noise compensation scheme is used to generate a constant delay even under the power supply line noise. The circuit was applied to a 4 Mbit dynamic RAM (DRAM) peripheral circuit. As a result, timing loss as well as malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time, compared with a conventional design using normal inverter chains, have been achieved

Keywords

cellular arrays; delay circuits; integrated memory circuits; random-access storage; 4 Mbit; CR-delay circuit technology; access time; asynchronicity; constant delay; cycle time; fast access time; high-speed DRAMs; malfunction; memory cell array; noise compensation scheme; peripheral circuits; power supply line noise; process conditions; timing loss; Capacitance; Chromium; Circuit noise; DRAM chips; Delay effects; Noise generators; Power generation; Power supplies; Random access memory; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.34069

Filename

34069