A 5 V only one-transistor 256 K EEPROM with page-mode erase

Author

Nakayama, Takeshi ; Miyawaki, Yoshikazu ; Kobayashi, Kazuo ; Terada, Yasushi ; Arima, Hideaki ; Matsukawa, Takayuki ; Yoshihara, Tsutomu

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

24

Issue

4

fYear

1989

fDate

8/1/1989 12:00:00 AM

Firstpage

911

Lastpage

915

Abstract

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7×8 μm² and the chip size is 5.55×7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC

Keywords

CMOS integrated circuits; EPROM; VLSI; error correction; integrated memory circuits; tunnelling; 1.5 micron; 256 kbit; 5 V; ECC; EEPROM; chip size; electron tunneling; error checking; memory cell size; n-well CMOS process; page-mode erase; parity bits; program-inhibiting voltages; programming; single metal layer; unselected bit lines; unselected cells; CMOS process; EPROM; Electrons; Error correction codes; Nonvolatile memory; Plastic packaging; Size control; Testing; Tunneling; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.34070

Filename

34070