Title :
A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip
Author :
Ida, Masao ; Kato, Naoki ; Takada, Tohru
Author_Institution :
NTT LIS Lab., Kanagawa, Japan
fDate :
8/1/1989 12:00:00 AM
Abstract :
A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n+-layer technology (FG-SAINT process)
Keywords :
III-V semiconductors; flip-flops; large scale integration; multiplexing equipment; 4 Gbit/s; FG-SAINT process; GaAs; LSI; data rates; flat-gate self-aligned implantation; master-slave D-flip-flop; multilayer ceramic package; multiplexer/demultiplexer chip; n+-layer technology; power layers; tristage type; Ceramics; Counting circuits; Distributed parameter circuits; Gallium arsenide; Large scale integration; Latches; Multiplexing; Packaging; Pins; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
