Title :
The inadequacy of the stuck-at fault model for testing mos lsi circuits: a review of mos failure mechanisms and some implications for computer-aided design and test of mos lsi circuits
Author :
Burgess, N. ; Damper, R.I.
Author_Institution :
University of Southampton, Department of Electronics & Information Engineering, Southampton, UK
fDate :
4/1/1984 12:00:00 AM
Abstract :
The stuck-at fault model is widely used as the basis for automatic test pattern generation in digital circuit testing, for example the D-algorithm. However, there have been growing doubts over the ability of the model to cover faults that occur in MOS LSI circuits. The paper consists of a review of the failure mechanisms that produce faults in MOS LSI circuits, a discussion of the problems that arise when using the stuck-at fault model to test MOS LSI circuits and a set of guidelines for the future development of computer-aided design and test of such circuits.
Keywords :
circuit CAD; fault location; field effect integrated circuits; integrated circuit testing; large scale integration; D-algorithm; MOS LSI circuits; automatic test pattern generation; computer aided testing; computer-aided design; digital circuit testing; failure mechanisms; stuck-at fault model; testing;
Journal_Title :
Software & Microsystems
DOI :
10.1049/sm.1984.0011