Title :
A 20 kbit associative memory LSI for artificial intelligence machines
Author :
Ogura, Takeshi ; Yamada, Junzo ; Yamada, Shin-Ichiro ; Tan-No, Masa-Aki
Author_Institution :
NTT LIS Lab., Kanagawa, Japan
fDate :
8/1/1989 12:00:00 AM
Abstract :
A 20 kb (512 words×40 b) CMOS associative-memory LSI is described. This LSI performs large-scale parallelism for highly efficient associative operations in artificial intelligence machines. Relational search, large-bit-length data treatment, and quick garbage collection are realized on the single-chip associative-memory LSI. A cell array structure has been designed in order to reduce the chip area. A newly designed simple accelerator circuit allows for high-speed search operations. The LSI is fabricated using 1.2 μm double-aluminium-layer CMOS process technology. 284000 devices have been integrated on a 5.3×7.9 mm2 chip. The measured minimum cycle time and power dissipation at 10 MHz operation are 85 ns and 250 mW, respectively. The associative memory, with its highly efficient associative operation capabilities, promises to be a large step toward the development of high-performance artificial intelligence machines
Keywords :
artificial intelligence; content-addressable storage; integrated memory circuits; large scale integration; 1.2 micron; 20 kbit; 250 mW; 85 ns; CMOS; artificial intelligence machines; associative memory LSI; cell array structure; garbage collection; large-bit-length data treatment; large-scale parallelism; minimum cycle time; power dissipation; relational search; Artificial intelligence; Associative memory; CMOS process; CMOS technology; Integrated circuit technology; Large scale integration; Large-scale systems; Power measurement; Semiconductor device measurement; Time measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
