An 8 ns 256 K BiCMOS RAM

A 256 K word×1 bit emitter-coupled logic (ECL) RAM, which achieves an 8 ns address access time, less than 400 mW power consumption at 50 MHz operation, and 150 mW at standby mode, is presented. To achieve an address access time of less than 10 nss and high packing density, an advanced 1.0 μm high-performance bipolar CMOS (Hi-BiCMOS) technology is used. A 9 GHz bipolar transistor cutoff frequency, 0.26 ns ECL gate propagation delay time, and 0.35 ns BiCMOS gate have been obtained. A 1.0 μm design rule permits layout of an NMOS memory cell with a high-resistance polysilicon load in 54.7 μm² and a 4.09×8.60 mm² chip. High performance is achieved by an optimized circuit design using a new input buffer, a BiCMOS decoder, and a high-speed bipolar sense amplifier. An active pull-down emitter-follower circuit and a BiCMOS current mirror ECL-MOS level shift circuit improve input buffer delay to less than 1.8 ns. A power-down technique has been studied to reduce standby power. Some experimental results are presented. High-speed address access is observed over a wide operational range