Title :
Analysis and reduction of sense-amplifier offset
Author_Institution :
Fac. of Electrotech., Univ. der Bundeswehr Munchen, Neubiberg, West Germany
fDate :
8/1/1989 12:00:00 AM
Abstract :
The offset of sense amplifiers used for dynamic RAMs (DRAMs) at the megabit level is investigated. An analytic expression which permits an easy calculation of the different offset contributions is derived. The influence of the transistor size and the effect of decoupling devices between bit lines and amplifier are discussed. The sensitivity can be improved if a preamplifier is used. Here, a circuit that doubles the sense signals by switching two capacitors between bit line and reference line is presented. The performance of the preamplifier has been verified through its realization on a test chip
Keywords :
integrated memory circuits; preamplifiers; random-access storage; bit lines; decoupling devices; dynamic RAMs; megabit level; preamplifier; reference line; sense-amplifier offset; transistor size; Circuit testing; Equations; Flip-flops; Helium; MOS devices; MOSFETs; Preamplifiers; Random access memory; Signal restoration; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
