A 1 kbit Josephson random access memory using variable threshold cells

The variable-thresholds cell has the advantages of simple structure and small size. In order to achieve nondestructive readout, rewriting has been carried out with peripheral circuits consisting of latching logic gates without any superconducting loop. OR-INVERT address decoders powered by a two-phase supply are used instead of the AND decoders of previous Josephson RAM chips. The 1 kbit (256×4 bit) RAM chip was fabricated using an Nb/Al-oxide/Nb tunnel junction technology with a 3 μm design rule. Experimental results show no failure in the 1028 logic gates of the peripheral circuits, and only a 2% bit failure in the cell plane of 1024 bits. Total power dissipation of the chip, including peripheral logic circuits, is 1.9 mW. A preliminary measurement yields an access time of about 500 ps