A new CMOS NAND logic circuit for reducing hot-carrier problems

The circuit, which uses a design concept called the self-bootstrapping method (SBM), lowers the channel electric field in the n-MOSFET during switching transients, leading to the suppression of the n-MOSFET substrate current. Experimental and simulation results show that about 3.9 times smaller peak substrate current is obtained in the NAND logic circuits with SBM when compared to the conventional NAND logic circuit. The circuit also gives shorter rise and fall times and better noise margin. The SBM concept provides highly reliable CMOS NAND logic without any change in device structure and/or fabrication process