CMOS open-fault detection in the presence of glitches and timing skews

A testable CMOS design technique in which some extra transistors are used in such a way that the CMOS gate is converted to a pseudo-nMOS/pMOS gate during testing is discussed. With the proposed design technique, CMOS open faults can be detected regardless of timing skews/delays, glitches, or charge sharing among the internal nodes. The major advantage of the proposed testable design technique is that it allows the use of a single test vector to detect a stuck-open fault. This significantly reduces the complexity of test generation and the time consumed for testing. The design procedure is simple and all the classical algorithms and automatic test-pattern-generating programs can be used to generate tests for circuits designed according to this technique. Even random testing techniques can be used efficiently to detect the open faults in these CMOS circuits