S/370 sign-magnitude floating-point adder

Author

Vassiliadis, Stamatis ; Lemon, David S. ; Putrino, Michael

Author_Institution

IBM Corp., Endicott, NY, USA

Volume

24

Issue

4

fYear

1989

fDate

8/1/1989 12:00:00 AM

Firstpage

1062

Lastpage

1070

Abstract

A 56 bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39×7.39 mm², and it is mounted on a metallized ceramic substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 Model 60 (9375) engineering scientific accelerator card

Keywords

NAND circuits; adders; bipolar integrated circuits; carry logic; integrated logic circuits; IBM 9370 Model 60; NAND gates; S/370; carry lookahead scheme; chip die size; end-around carry; engineering scientific accelerator card; error-detecting logic; four-level metal bipolar master-slice technology; metallized ceramic substrate; sign-magnitude floating-point adder; Algorithm design and analysis; Automatic logic units; Ceramics; Fault detection; Helium; Registers; Senior members;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.34093

Filename

34093