A new phase-locked loop used in a frequency synthesizer

A well-known contradiction in phase-locked frequency synthesizer design is between frequency resolution, on the one hand, and bandwidth of the phase-locked loop (PLL), on the other. To solve this problem, a technique that uses an algorithm that produces a group of different divide numbers to the programmable feedback frequency divider of PLL for each required output frequency is presented. The interference frequency at the output of the phase detector of PLL and the frequency resolution can then be set independent of each other. High resolution and wide bandwidth are achieved simultaneously, with a simple synthesizer design leading to savings in power consumed and device cost