Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

A simple top-down method for realizing an array of vertically stacked nanowires is presented. The process utilizes the nonuniformity in inductively coupled plasma (ICP) etching to form a scallop pattern at the sidewall of a tall silicon ridge that is further trimmed to form stacked nanowires by stress-limited oxidation. The process has been demonstrated to be controllable and repeatable, starting with bulk silicon wafers. Vertically stacked gate-all-around MOSFETs have been fabricated, which show excellent performance with a nearly ideal subthreshold slope of 62 mV/dec, a low leakage current, and a high I _on/I _off ratio of ~ 10⁸.