• DocumentCode
    1218870
  • Title

    A fast resolving BiNMOS synchronizer for parallel processor interconnect

  • Author

    Jex, Jerry ; Dike, Charles

  • Author_Institution
    Intel Corp., Hillsboro, OR, USA
  • Volume
    30
  • Issue
    2
  • fYear
    1995
  • fDate
    2/1/1995 12:00:00 AM
  • Firstpage
    133
  • Lastpage
    139
  • Abstract
    The design, testing, and application of a BiNMOS metastability resolving synchronizer is described. High speed signaling requires multiple clock cycle metastability settling time. The integrated circuit provides low tau (fast resolution) and is considered one of the fastest synchronizers available to date. The circuit reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle. High gain-bandwidth product is accomplished with n-p-n transistors driving a cross-coupled inverter latch with reduced node capacitance. Longer settling time is provided by omitting metastability immune circuitry and using a parallel staged synchronizer
  • Keywords
    BIMOS integrated circuits; digital integrated circuits; failure analysis; integrated circuit testing; multiprocessor interconnection networks; parallel processing; synchronisation; BiNMOS synchronizer; cross-coupled inverter latch; fast resolving synchronizer; high gain-bandwidth product; high speed signaling; integrated circuit; metastability resolving synchronizer; metastability settling time; multiple clock cycle; n-p-n transistors; node capacitance reduction; parallel processor interconnect; parallel staged synchronizer; synchronisation failure; testing; Bandwidth; Circuit testing; Clocks; Delay; Frequency synchronization; Integrated circuit interconnections; Latches; Metastasis; Sampling methods; Signal resolution;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.341740
  • Filename
    341740