A new, precharged, low-power logic family for GaAs circuits

Author

Chandramouli, V. ; Michell, Nick ; Smith, Kent F.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

30

Issue

2

fYear

1995

fDate

2/1/1995 12:00:00 AM

Firstpage

140

Lastpage

143

Abstract

We present a new precharged, low-power logic family in GaAs that operates at speeds comparable to DCFL and consumes about one-fourth the power of DCFL. It uses a 2 V power supply for operation and can be used in conjunction with the widely used DCFL circuits. The logic family allows us to build complex gates in one gate delay, provides better noise margins, and is less susceptible to load capacitances than an unbuffered DCFL gate, thus making it useful for standard-cell based designs. To verify the approach, we have designed and fabricated a fully functional test chip containing a precharged full adder

Keywords

III-V semiconductors; adders; digital arithmetic; field effect logic circuits; gallium arsenide; integrated circuit noise; 2 V; GaAs; GaAs circuits; load capacitances; low-power logic family; noise margins; precharged full adder; precharged logic family; standard-cell based designs; Adders; Capacitance; Circuit noise; Computer science; Delay; Gallium arsenide; Logic circuits; Logic design; Power supplies; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.341741

Filename

341741