DocumentCode :
1219834
Title :
A VLSI design for computing exponentiations in GF(2m) and its application to generate pseudorandom number sequences
Author :
Wang, Charles C. ; Pei, Dingyi
Author_Institution :
Jet Propulsion Lab., Pasadena, CA, USA
Volume :
39
Issue :
2
fYear :
1990
fDate :
2/1/1990 12:00:00 AM
Firstpage :
258
Lastpage :
262
Abstract :
A VLSI design for computing exponentiation in finite fields is developed. An algorithm to generate a relatively long pseudorandom number sequence is presented. It is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme
Keywords :
VLSI; logic CAD; multiplying circuits; random number generation; VLSI design; computing exponentiations; finite fields; pseudorandom number sequences; Circuits; Computer architecture; Cryptography; Galois fields; Laboratories; Propulsion; Shift registers; Signal generators; Space technology; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.45211
Filename :
45211
Link To Document :
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