A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications

The FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. This paper proposes a technique to reduce the power consumption of a popular low power radix-4 pipelined FFT processor by modifying its operation sequence. The complex multiplier is one of the most power consuming blocks in the FFT processor. The switching activity at its fixed coefficient input, and hence its power consumption, can be drastically reduced by coefficient ordering. Coefficient ordering requires a novel commutator architecture which can handle the corresponding data sequencing as per new coefficient ordering. The resulting power saving is around 23% and 9%, respectively, for the 16-point and 64-point radix-4 pipelined FFT processor. This approach is very attractive for orthogonal frequency division multiplexing (OFDM) based wireless LAN (IEEE 802.11) requiring short FFTs but it can also be applied to the penultimate stage of longer FFTs used in digital audio and video broadcasting.