Title :
A low-permittivity interconnection using an SiBN interlayer
Author :
Maeda, Masahiko ; Makino, Takahiro ; Yamamoto, Ei-ichi ; Konaka, Shinsuke
Author_Institution :
NTT LSI Lab., Kanagawa, Japan
fDate :
9/1/1989 12:00:00 AM
Abstract :
A low-permittivity two-level interconnection process is presented. The key features of this process are the use of a low dielectric constant SiBN interlayer and the adoption of planarization using a two-stage etch-back process. The SiBN film is characterized from the standpoint of its device applications. The two-level interconnection process flow is described in detail. The effect of the SiBN interlayer in reducing the second wiring capacitance is compared to that of a conventional silicon nitride interlayer. This is demonstrated by fabricating a 33-stage ECL ring oscillator and a 2.1 kG macrocell array LSI
Keywords :
VLSI; bipolar integrated circuits; chemical vapour deposition; dielectric thin films; emitter-coupled logic; integrated circuit technology; integrated logic circuits; metallisation; oscillators; silicon compounds; 33-stage ECL ring oscillator; SiBN film; SiBN interlayer; device applications; features; low-permittivity interconnection; macrocell array LSI; planarization; two-level interconnection process; two-stage etch-back process; wiring capacitance reduction; Atomic measurements; Capacitance; Dielectric constant; Dielectrics and electrical insulation; Large scale integration; Macrocell networks; Ring oscillators; Semiconductor films; Silicon; Wiring;
Journal_Title :
Electron Devices, IEEE Transactions on
