A path to 10% efficiency for tin sulfide devices

We preform device simulations of a tin sulfide (SnS) device stack using SCAPS to define a path to 10% efficient devices. We determine and constrain a baseline device model using recent experimental results on one of our 3.9% efficient cells. Through a multistep fitting process, we find a conduction band cliff of -0.2 eV between SnS and Zn(O,S) to be limiting the open circuit voltage (V_OC). To move towards a higher efficiency, we can optimize the buffer layer band alignment. Improvement of the SnS lifetime to >1 ns is necessary to reach 10% efficiency. Additionally, absorber-buffer interface recombination must be suppressed, either by reducing recombination activity of defects or creating a strong inversion layer at the interface.