Title :
A new soft-error-immune static memory cell having a vertical driver MOSFET with a buried source for the ground potential
Author :
Minami, Masataka ; Wakui, Yookoo ; Matsuki, Hiroshi ; Nagano, Takahiro
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
fDate :
9/1/1989 12:00:00 AM
Abstract :
A small-area static memory cell with high soft-error immunity is proposed. The driver MOSFET has a vertical structure. Its source region is buried in the substrate to which the ground potential is applied on order to shield the surface drain region from noise charges. The transfer MOSFET is a lateral type. These changes result in a reduction of the memory cell size and the gate area with the same effective gate width, since the channel is formed around the trench gate electrode. High soft error immunity is also expected because the drain region is shielded from noise charges induced by a-particles. A test circuit for a 1-bit memory cell was fabricated by using the 1.3 μm process technology. The cell size was 0.75 times as large as the conventional memory cell size, and its soft error rate was only 0.04 times that of the conventional one. The results show that this memory cell is suitable for future multimegabit SRAMs
Keywords :
MOS integrated circuits; VLSI; alpha-particles; integrated circuit technology; integrated memory circuits; random-access storage; 1-bit memory cell; 1.3 micron; ULSI; alpha particles; buried source; cell area reduction; ground potential; high soft-error immunity; memory cell size; multimegabit SRAMs; small-area static memory cell; soft error rate; soft-error-immune static memory cell; test circuit; transfer MOSFET; trench gate electrode; vertical driver MOSFET; Circuit noise; Circuit testing; Driver circuits; Electrodes; Equivalent circuits; Error analysis; MOSFET circuits; Parasitic capacitance; Random access memory; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
