Title :
Vertical scalability of forward delay times in bipolar transistors
Author :
Castaner, L. ; Ashburn, P.
Author_Institution :
Dept. of Electron. Eng., Univ. of Polytech. Cataluna, Barcelona, Spain
fDate :
9/1/1989 12:00:00 AM
Abstract :
Analytical expressions for the emitter and base forward delay times of a bipolar transistor are derived. The delay times are written in terms of a set of integrals, which allow the dependence on vertical device dimensions to be explicitly stated. These integrals are related to the heavy doping parameters and are valid for arbitrary base and emitter profiles. Simple analytical equations incorporating these integrals can then be used to calculate the delay times
Keywords :
bipolar integrated circuits; bipolar transistors; delays; integral equations; semiconductor device models; base integrals; bipolar transistors; charge storage; emitter integrals; forward delay times; heavy doping parameters; vertical device dimensions; vertical scalability; Analog memory; Bipolar transistors; Circuits; Delay; EPROM; Nonvolatile memory; Pins; Scalability; Temperature dependence; Threshold voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
