• DocumentCode
    1221218
  • Title

    Vertical scalability of forward delay times in bipolar transistors

  • Author

    Castaner, L. ; Ashburn, P.

  • Author_Institution
    Dept. of Electron. Eng., Univ. of Polytech. Cataluna, Barcelona, Spain
  • Volume
    36
  • Issue
    9
  • fYear
    1989
  • fDate
    9/1/1989 12:00:00 AM
  • Firstpage
    1841
  • Lastpage
    1844
  • Abstract
    Analytical expressions for the emitter and base forward delay times of a bipolar transistor are derived. The delay times are written in terms of a set of integrals, which allow the dependence on vertical device dimensions to be explicitly stated. These integrals are related to the heavy doping parameters and are valid for arbitrary base and emitter profiles. Simple analytical equations incorporating these integrals can then be used to calculate the delay times
  • Keywords
    bipolar integrated circuits; bipolar transistors; delays; integral equations; semiconductor device models; base integrals; bipolar transistors; charge storage; emitter integrals; forward delay times; heavy doping parameters; vertical device dimensions; vertical scalability; Analog memory; Bipolar transistors; Circuits; Delay; EPROM; Nonvolatile memory; Pins; Scalability; Temperature dependence; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.34251
  • Filename
    34251
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1221218