Title :
AC-and DC-powered subnanosecond 1-kbit Josephson cache memory design
Author :
Wada, Yoshifusa ; Hidaka, Mutsuo ; Nagasawa, Shuichi ; Ishida, Ichiro
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators.<>
Keywords :
Josephson effect; buffer storage; superconducting junction devices; superconducting memory circuits; 1 kbit; 570 ps; AC powered memory; DC-powered memory; Josephson cache memory; Pb-alloy process; address decoders; address line drivers; bipolar current drive; four-flux-quanta storage loop; fully decoded memory; inductor coupled gates; magnetic flux trapping; read access time; resistor-coupled Josephson logic circuits; sense circuits; sub-nanosecond access time; superconducting quantum interface device; three-junction symmetric SQUID; Cache memory; Decoding; Driver circuits; Inductors; Josephson junctions; Magnetic circuits; Magnetic flux; SQUIDs; Superconducting devices; Superconducting logic circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
