Title :
The effect of dimensional scaling on the erase characteristics of NOR flash memory
Author_Institution :
Memory Div., Samsung Electron. Co. Ltd., Yong-In, South Korea
fDate :
4/1/2003 12:00:00 AM
Abstract :
In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim tunneling characteristics due to a coupling ratio variation, resulting in a much broader erase threshold distribution. Theoretical analysis including MEDICI simulations confirms the effects of parasitic capacitance on the erase threshold of NOR flash cells.
Keywords :
NOR circuits; cellular arrays; circuit simulation; flash memories; tunnelling; Fowler-Nordheim tunneling characteristics; MEDICI simulations; NOR flash memory; bitline contact; cell scaling; coupling ratio variation; dimensional scaling; erase characteristics; erase threshold distribution; floating gate; parasitic capacitance; Analytical models; Associate members; Flash memory; Interference; Medical simulation; Nonvolatile memory; Parasitic capacitance; Testing; Threshold voltage; Tunneling;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.810882