Author :
Baird, S.A. ; Bains, N. ; Campbell, D. ; Cawthraw, M. ; Charlton, D. ; Coughlan, J. ; Eisenhandler, E. ; Ellis, N. ; Fensome, I. ; Flynn, P. ; Galagadera, S. ; Garvey, J. ; Grayer, G. ; Gregory, J. ; Halsall, R. ; Jimack, M.P. ; Jovanovic, P. ; Kenyon, I.
Author_Institution :
Rutherford Appleton Lab., Chilton, Didcot, UK
Abstract :
The UA1 first level trigger processor (TP) is a fast digital machine with a highly parallel pipelined architecture of fast combinational and programmable transistor-transistor logic controlled by programmable microsequencers. The TP uses 100000 ICs (integrated circuits) housed in 18 crates each containing 21 FASTBUS-sized molecules. It is hardwired with a very high level of interconnection. The energy deposited in the upgraded calorimeter is digitized into 1700 bytes of input data every beam crossing (3.8 μs). The processor selects in 1.5 μs events for further processing (1 in 30000). The trigger has improved hadron jet rejection, achieved by requiring low-energy deposition around the electromagnetic cluster. A missing-transverse-energy trigger and a total-energy trigger have also been implemented
Keywords :
calorimeters; multiprocessing systems; physics computing; signal processing equipment; special purpose computers; 1.5 mus; 1700 B; 3.8 mus; FASTBUS; UA1 first level trigger processor; hadron jet rejection; missing-transverse-energy trigger; parallel pipelined architecture; programmable microsequencers; total-energy trigger; transistor-transistor logic; Architecture; Educational institutions; Electrons; Fastbus; Laboratories; Mesons; Poles and towers; Programmable control; Programmable logic arrays; Programmable logic devices;
