Title :
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer
Author :
Kim, Jinwook ; Yang, Jeongsik ; Byun, Sangjin ; Jun, Hyunduk ; Park, Jeongkyu ; Conroy, Cormac S G ; Kim, Beomsup
Author_Institution :
Berkana Wireless Inc., Campbell, CA, USA
Abstract :
This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5×10-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.
Keywords :
CMOS integrated circuits; adaptive equalisers; delays; jitter; least mean squares methods; transceivers; 0.18 micron; 1.8 V; 10 Gbit; 178 mW; CMOS technology; bit-error rate; clock data recovery circuit; extended attachment unit interface; four-channel CMOS; high-speed operation; low-jitter delay; mixed-mode adaptive equalizer; mixed-mode least-mean-square; quad-channel serial-link transceiver; recovered clock; Adaptive equalizers; Bit error rate; CMOS technology; Circuits; Clocks; Delay; Jitter; Least squares approximation; Power supplies; Transceivers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.841037
