High-performance low-power dual transition preferentially sized (DTPS) logic

We present a dual transition preferentially sized (DTPS) logic that uses two separate paths - one for the fast propagation of low-to-high signal and the other for fast propagation of high-to-low signal. DTPS logic is suitable for multistage buffers and critical sections of datapaths requiring good noise immunity and low power dissipation while achieving high performance. We derived formulas to obtain optimal tapering factors of multistage buffers based on preferentially sized (PS) inverters, and implemented DTPS logic using the optimal tapering factors. We fabricated datapaths based on static CMOS logic, domino logic, and DTPS logic in 0.18-μm technology. DTPS logic shows 15% and 16% improvements in performance and power dissipation, respectively, over domino, and 42% improvement in performance compared to static CMOS.