Title :
Low standby power state storage for sub-130-nm technologies
Author :
Clark, Lawrence T. ; Ricci, Franco ; Biyani, Manish
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Abstract :
Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process.
Keywords :
integrated circuit design; leakage currents; power consumption; sequential circuits; 90 nm; active power consumption; circuit design; circuit operation; dynamic circuits; functional integration; high-performance transistors; leakage current; low standby power state storage; low-leakage thick-gate shadow latches; process scaling; pulse-clocked latches; sequential logic circuits; Batteries; Circuit synthesis; Dynamic voltage scaling; Energy consumption; Frequency; Latches; Leakage current; Power supplies; Threshold voltage; Tunneling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.840987
