Front end and signal processing electronics for large detectors

The design of front-end electronic systems for experiments at very-high-interaction-rate colliding beams and fixed-target accelerators is discussed. Consideration is given to the preamplifier and shaping amplifier design, and to the optimal choice of technology, with particular emphasis on detectors with source capacitance in the range of 1-30 pF and for shaping times of 3-20 ns. Possible architectures of a two-level, on-chip buffering system which enable simultaneous, asynchronous data acquisition and readout with nearly no deadtime are discussed. Emphasis is placed on minimal power dissipation. A system of drift chamber electronics, with the goals of time resolution <0.5 ns and double pulse resolution of 20-30 ns, is considered as an example. Design options which minimize the necessity of calibration are presented