A low power low noise amplifier for a 128 channel detector read-out chip

Author

Stanton, J.C.

Author_Institution

Rutherford Appleton Lab., Chilton, Didcot, UK

Volume

36

Issue

1

fYear

1989

fDate

2/1/1989 12:00:00 AM

Firstpage

522

Lastpage

527

Abstract

The design of a low-power, low-noise CMOS (complementary metal oxide semiconductor) amplifier is described. The amplifier was designed using the folded cascode configuration and was implemented on a 3-μm double polysilicon process. The amplifier is part of a 128-channel charge amplifier array chip for use in the readout of radiation detectors with many channels. Aspects of the amplifier design such as bandwidth, pulse response, and noise are discussed, and the effects of individual transistors are shown, thereby relating circuit performance to process parameters. Circuit and radiation test results are included. The results show that a noise level as low as 670 electrons has been achieved with a risetime of 240 ns and a power density of less than 0.45 mW per channel

Keywords

CMOS integrated circuits; amplifiers; linear integrated circuits; nuclear electronics; 240 ns; 3 micron; CMOS; amplifier; bandwidth; charge amplifier array chip; circuit performance; complementary metal oxide semiconductor; double polysilicon process; folded cascode configuration; noise; power density; process parameters; pulse response; radiation detectors; radiation test results; risetime; transistors; Bandwidth; Circuit noise; Circuit testing; Low-noise amplifiers; Pulse amplifiers; Pulse circuits; Radiation detectors; Semiconductor device noise; Semiconductor optical amplifiers; Sensor arrays;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.34494

Filename

34494