DocumentCode
1223702
Title
TMC-a CMOS time to digital converter VLSI
Author
Arai, Y. ; Ohsugi, T.
Author_Institution
KEK, Nat. Lab. for High Energy Phys., Ibaraki, Japan
Volume
36
Issue
1
fYear
1989
fDate
2/1/1989 12:00:00 AM
Firstpage
528
Lastpage
531
Abstract
A novel time-to-digital converter CMOS VLSI chip has been developed. The main components of this TMC are memories and delay lines (buffers in series). Low-power and high-density characteristics have been attained by a submicron CMOS process and a novel circuit scheme utilizing variable-delay elements with a feedback circuit. Test results of a prototype are described, with attention given to delay time, linearity, and stability
Keywords
CMOS integrated circuits; VLSI; analogue-digital conversion; digital integrated circuits; nuclear electronics; buffers; delay lines; delay time; feedback circuit; linearity; memories; stability; submicron CMOS process; time-to-digital converter CMOS VLSI chip; variable-delay elements; Circuit testing; Clocks; Delay effects; Delay lines; Feedback circuits; Pulse inverters; Pulse width modulation inverters; Silicon; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/23.34495
Filename
34495
Link To Document