Title :
A FASTBUS flash ADC system for the mark II vertex chamber
Author_Institution :
Stanford Linear Accelerator Center, Stanford Univ., CA, USA
fDate :
2/1/1989 12:00:00 AM
Abstract :
The author gives a description of a flash ADC system built for the Mark II experiment at the Stanford Linear Accelerator Center (SLAC). This system was designed for use in the experiment´s vertex chamber where signals could occur over a relatively long time, approximately 10 microseconds. This long time, coupled with fast cable amplifiers, necessitated an alternate design approach than was used with a dE/dX FASTBUS flash ADC design
Keywords :
analogue-digital conversion; nuclear electronics; particle detectors; physics computing; Mark II experiment; fast cable amplifiers; flash ADC system; vertex chamber; Cable shielding; Clocks; Detectors; Fastbus; Frequency; Linear accelerators; Operational amplifiers; Signal design; Signal processing; Timing;
Journal_Title :
Nuclear Science, IEEE Transactions on
