• DocumentCode
    1223948
  • Title

    A fast integrating eight-bit bilinear ADC

  • Author

    Biery, K.A. ; Quimette, D.A. ; Ritchie, J.L.

  • Author_Institution
    Dept. of Phys., Stanford Univ., CA, USA
  • Volume
    36
  • Issue
    1
  • fYear
    1989
  • fDate
    2/1/1989 12:00:00 AM
  • Firstpage
    650
  • Lastpage
    652
  • Abstract
    A fast gated charge integrating ADC has been developed for measuring short photomultiplier pulses at very high event rates. The circuit is bilinear with 100 pC full scale and a least count of 150 fC. It features DC coupling, a minimum gate width of 20 ns, a minimum time between events of 200 ns plus gate width, a two event buffer and front-end zero suppression with 100 ns read time per hit channel. Five hundred channels have been built and installed in the rare K L0 decay experiment E791 at Brookhaven National Laboratory
  • Keywords
    analogue-digital conversion; nuclear electronics; physics computing; scintillation counters; 100 ns; 20 ns; 200 ns; 8 bit; E791; fast gated charge integrating ADC; front-end zero suppression; gate width; short photomultiplier pulses; two event buffer; Coupling circuits; Dynamic range; Event detection; Laboratories; Linear accelerators; Photomultipliers; Physics; Radiation detectors; Scintillation counters; Signal detection;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.34519
  • Filename
    34519
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1223948