A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method

Author

Cho, Seongjae ; Park, Il Han ; Kim, Yoon ; Park, Se Hwan ; Lee, Jong Duk ; Shin, Hyungcheol ; Park, Byung-Gook

Author_Institution

Sch. of Electr. Eng. (SoEE) & Comput. Sci., Seoul Nat. Univ. (SNU), Seoul, South Korea

Volume

8

Issue

5

fYear

2009

Firstpage

595

Lastpage

602

Abstract

In this study, a nonvolatile memory (NVM) device of novel structure in three-dimension is introduced and validated. It is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between silicon pillars can be reduced, in which additional gates called cutoff gates realize perfect operations. Gated twin-bit (GTB) NVM device is considered as the ultimate form of 3-D NVM device based on double-gate structure in a sense that the use of common gate makes maximal integration possible. The operation schemes and fabrication method of the GTB NVM device are also introduced.

Keywords

elemental semiconductors; random-access storage; semiconductor device manufacture; semiconductor storage; silicon; 3D NVM device; cutoff gates; device fabrication; double-gate structure; gated twin-bit nonvolatile memory device; memory nodes; pillar structure; silicon pillars; single control gate; storage nodes; 3-D nonvolatile memory (NVM) device; cutoff gate; double-gate structure; gated twin-bit (GTB); pillar structure;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2009.2019641

Filename

4810110