IEEE P1596, a scalable coherent interface for gigabyte/sec multiprocessor applications

IEEE P1596, the scalable coherent interface (SCI), formerly known as SuperBus is based on experience gained during the development of FASTBUS (IEEE 960), Futurebus (IEEE 896.1) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 Gb/s per processor; efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters, and general switched interconnections like Banyan, Omega, or full crossbar networks. To achieve these goals, SCI must sacrifice the immediate handshake characteristics of the present generation of buses in favour of a packetlike split-cycle protocol. Wire-ORs, broadcasts, and even ordinary passive bus structures must be avoided. However, a lower performance (1 Gb/s per backplane instead of per processor) implementation using a register insertion ring architecture on a passive backplane appears to be possible using the same interface as for the more costly switch networks. The author summarizes current directions and reports the status of the work in progress