Title :
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC
Author :
Hong, Hao-Chiao ; Lee, Guo-Ming
Author_Institution :
Nat. Chiao Tung Univ., Hsinchu
Abstract :
An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 muW in the test, corresponding to a figure of merit of 65 f J/conversion-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; bandwidth allocation; distortion; integrated circuit design; low-power electronics; CMOS application; Nyquist bandwidth; analog-to- digital converter; bandwidth 100 kHz; bootstrapped switch; effective resolution bandwidth; low power; noise figure 47.4 dB; power 2.4 muW; signal-to-noise-and-distortion ratio; size 0.18 micron; successive approximation; voltage 0.9 V; Analog circuits; Bandwidth; Circuit synthesis; Costs; Energy efficiency; Energy resolution; Low voltage; MOSFETs; Switches; Threshold voltage; $mu$W design; ADC; energy efficient; low power; low supply voltage; successive approximation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.905237
