Performance Enhancement of Switched-Current Technique Using Subthreshold MOS Operation

The general performance of class AB switched currents (SI) is analyzed using the general MOS equations valid for all regions of operation. Using a figure-of-merit combining speed, dynamic range, and power consumption, the overall performance is shown to improve progressively as the SI memory transistors´ operating region is moved from strong inversion to moderate and then weak inversion. The analysis is validated first by experiment using transistor arrays and then by simulation using 0.35-mum, 0.18-mum, and 90-nm CMOS process data. After discussing nonideal behavior of the weak inversion memory cell, the following two practical designs are described: a cascoded class AB memory at 1.25-V supply in the 3.3-V 0.35-mum process and a two-step sampling class AB memory at 0.6-V supply in the 1.8-V 0.18-mum process, and each demonstrates good performance.