DocumentCode
1225514
Title
Correction to “A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC”
Author
Pun, Kong-Pang ; Chatterjee, Saptarshi ; Kinget, Peter
Volume
42
Issue
10
fYear
2007
Firstpage
2315
Lastpage
2315
Abstract
In the above titled paper (ibid., vol. 42, no. 3, pp. 496-507, Mar 07), corrections were made to the schematic diagram of the two-stage OTA (Figure 11).
Keywords
Capacitors; Delta modulation; Joining processes; Operational amplifiers; Phase noise; Resistors; Solid state circuits; Transconductance;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2007.907184
Filename
4317711
Link To Document