Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to radiation-induced single-event-upsets (SEUs). Redundancy insertion has been adopted to provide the circuit with additional transient error resiliency. However, its applicability and efficiency are limited by the tight design constraints and budgets. In this paper, we present an intelligent ldquoconstraint-aware robustness insertionrdquo methodology. By selectively protecting sequential elements in static CMOS digital circuits, it is able to maximally improve the SEU tolerance while keeping the incurred design overhead within acceptable range. Our technique consists of three major components. The first one is a configurable hardening sequential cell design that serves as the basic building block of the framework; the second one is a robustness calibration technique that evaluates the relative error tolerance of all sequential elements and provides guidelines to the redundancy insertion; the third one is an optimization algorithm that searches for the optimal protection scheme under given design constraints and budgets. Simulation results show that the intelligent robustness insertion reduced the error rate by 46% with zero timing penalty and 10% area increase. Furthermore, by exploring the tradeoffs between reliability and design overhead, we also demonstrate the proposed technique can help achieve high reliability improvement while keeping the design overhead within acceptable range.