Test Set Development for Cache Memory in Modern Microprocessors

Author

AL-Ars, Zaid ; Hamdioui, Said ; Gaydadjiev, Georgi ; Vassiliadis, Stamatis

Author_Institution

Lab. of Comput. Eng., Delft Univ. of Technol., Delft

Volume

16

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

725

Lastpage

732

Abstract

Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize the test set used at Intel to test their 512-kB caches manufactured in a 0.13- mum technology. An example is shown where a maximal test set of 15 tests with a corresponding maximum test time of 160.942 ms/chip is optimized to only six tests that require a test time of only 30.498 ms/chip.

Keywords

cache storage; integrated circuit testing; microprocessor chips; Intel; cache memory; memory size 512 KByte; memory tests; microprocessors; size 0.13 mum; test on-chip cache; test set development; Cache memory; Computer science; Fault detection; Mathematics; Microprocessors; Optimization methods; Performance evaluation; Process design; Pulp manufacturing; System testing; Fault coverage; memory testing; microprocessor cache; test set development; test time;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2008.2000257

Filename

4526718